This invention relates to a semiconductor memory device whose unit memory cell is formed of an MOS transistor comprising a main electrode region, gate region and capacitor region arranged in the order mentioned.
High integration, high performance and low power consumption are demanded of a memory device constituted by a large number of integrated MOS transistors. A semiconductor memory device whose unit memory cell comprises a main electrode region, gate region and capacitor region arranged in the order mentioned and which is designed to act as a random access memory (hereinafter abbreviated as "RAM") has been known to be preferred as an element for meeting the aforesaid requirements.
For further development of a memory device whose unit memory cell is constructed as described above, it is necessary to carry out higher integration, than has been possible in the past, suppress a short channel effect arising from the unavoidable shortening of the channel of individual MOS transistors integrated with higher density, and increase the capacitance of the capacitor region. As used herein, the term "short channel effect" is defined to mean that where the MOS transistor is made compact, its channel is naturally shortened, resulting in an increase or decrease in gate threshold voltage. The short-channel effect is known to arise from the irregular distribution of an electric field in the gate region. Particularly where the short channel effect is of the type which tends to decrease the gate threshold voltage, then the difficulties occur in that undesirable conduction appears in the gate region or a charge stored in the capacitor of the capacitor region is likely to be lost. Further, where an attempt is made to narrow an area occupied by the MOS transistor by decreasing an area occupied by a capacitor electrode in the capacitor region, or to preserve a required amount of capacitance in the capacitor region by reducing the thickness of an insulation layer formed between the capacitor electrode and semiconductor substrate, then it is impossible to obtain the desired characteristics of insulation and withstand voltage.
For better understanding of this invention, there will now be described by reference to FIG. 1 the construction of the prior art MOS transistor used as a unit memory cell which comprises a main electrode region, gate region and capacitor region arranged in the order mentioned.
Referring to FIG. 1 illustrating the construction of the conventional MOS transistor Q, a main electrode region 1, gate region 2 and capacitor region 3 are formed in the order mentioned as viewed in the horizontal direction. Namely, an N.sup.+ semiconductor layer 5 constituting a drain region is formed on a P type silicon substrate 4 to be used as a digit line. In the gate region 2, a gate electrode 7 prepared from polycrystalline silicon is formed above the substrate 4 with a gate insulation layer 6 interposed therebetween. The capacitor region 3 corresponds to the source region of the ordinary MOS transistor. Provided above the capacitor region 3 is a capacitor electrode 9 with an insulation layer 8 deposited therebetween. The capacitor electrode 9 causes an inverted layer appearing on a depletion layer 4a occurring in the upper surface portion of the substrate 4 to constitute a capacitor C acting as the other electrode. Numeral 10 denotes an aluminium wire electrically connected to the gate electrode 7 to be used as a word line. FIG. 2 shows an equivalent circuit arrangement of, for example, the MOS transistor Q. This MOS transistor Q is formed of a main electrode region 1, gate region 2 and capacitor region 3 simply arranged in the horizontal direction. Where, therefore, an attempt is made to increase the capacitance of the capacitor region 3, it is necessary to enlarge an area occupied by the capacitor region 3 or reduce the thickness of the insulation layer 8. However, the enlargement of the area of the capacitor region 3 obstructs the high integration of a large number of unit memory cells. The decrease of the thickness of the gate insulation layer 6 presents difficulties in ensuring the characteristics of insulation and withstand voltage. Further, the shortening of the channel of the MOS transistor Q shown in FIG. 1 makes it difficult to provide the uniform distribution of an electric field below the channel of the MOS transistor Q, thus rendering the suppression of the short channel effect also difficult.
It is accordingly the object of this invention to provide a semiconductor memory device which enables the unit memory cell to maintain a desired MOS capacitance even when the unit memory cell is reduced in area, and moreover can effectively prevent the short-channel effect.